| File |
Title and Description  |
ID Number  |
Last Update  |
Software Downloads |
 |
Advantages of DDR2 Differential DQS SignalingAdvantages of DDR2 Differential DQS Signaling
- Focuses on the benefits the differential DQS signaling feature provides and explains how to design with it |
TN-47-23 |
2008-03-01T00:00:00-07:00Mar 2008 |
|
 |
DDR2 (Point-to-Point) Features and FunctionalityDDR2 (Point-to-Point) Features and Functionality
- Focuses on the unique memory requirements of point-to-point design layouts and describes DDR2 features and functionality. |
TN-47-19 |
2006-04-01T00:00:00-06:00Apr 2006 |
|
 |
DDR2 SDRAM Offers New Features and FunctionalityDDR2 SDRAM Offers New Features and Functionality
- Discusses the various changes in DDR2 technology and the resulting features and benefits |
TN-47-02 |
2006-06-01T00:00:00-06:00Jun 2006 |
|
 |
Calculating Memory System Power for DDR2Calculating Memory System Power for DDR2
- Details how DDR2 SDRAM consumes power and provides tools to estimate power consumption in a given system. |
TN-47-04 |
2006-06-01T00:00:00-06:00Jun 2006 |
|
 |
DDR2 Package Sizes and Layout RequirementsDDR2 Package Sizes and Layout Requirements
- Covers DDR2 package sizes and layout requirements |
TN-47-08 |
2005-11-01T00:00:00-06:00Nov 2005 |
|
 |
DDR2 SODIMM Optimized Address/Command NetsDDR2 SODIMM Optimized Address/Command Nets
- Provides the system-level designer with an overview of the DDR2 SODIMM family and offers insight into termination techniques utilized on the commands and addresses for these modules |
TN-47-17 |
2005-05-01T00:00:00-06:00May 2005 |
|
 |
High speed DRAM controller designHigh speed DRAM controller design
- Identifies and discusses five key areas of DRAM controller design |
TN-45-54 |
2008-04-01T00:00:00-06:00Apr 2008 |
|
 |
DDR2 (Point-to-Point) Package Sizes and Layout BasicsDDR2 (Point-to-Point) Package Sizes and Layout Basics
- General guidelines for developing the PCB floor plan. |
TN-47-20 |
2006-05-01T00:00:00-06:00May 2006 |
|
 |
Module Pinout DecoderModule Pinout Decoder
- Provides sorted pin assignment tables and pin location figures for use in DDR2 DIMM signal identification, tracing, and troubleshooting |
TN-47-03 |
2004-08-01T00:00:00-06:00Aug 2004 |
|
 |
Power Solutions for DDR2 Notebook PCsPower Solutions for DDR2 Notebook PCs
- Provides a general guideline for designing the DDR2 memory power circuitry |
TN-47-05 |
2004-06-01T00:00:00-06:00Jun 2004 |
|
| File |
Title and Description  |
ID Number  |
Last Update  |
Software Downloads |
 |
DDR2 Read InterruptDDR2 Read Interrupt
- Describes legal execution of a READ interrupted by a READ command |
TN-47-13 |
2004-12-01T00:00:00-07:00Dec 2004 |
|
 |
Designing for High-Density DDR2 MemoryDesigning for High-Density DDR2 Memory
- Focuses on designing for high-density memory—addressing schemes of each density, configurations, and the subtle differences between the 4-bank and new 8-bank DDR2 devices |
TN-47-16 |
2005-05-01T00:00:00-06:00May 2005 |
|
 |
FBDIMM – Channel Utilization (Bandwidth and Power)FBDIMM – Channel Utilization (Bandwidth and Power)
- Newly introduced FBDIMMs offer virtually unlimited scalability of density, a significantly reduced number of routed motherboard signals, and high bandwidth solutions, all with an extremely reliable channel protocol. |
TN-47-21 |
2006-10-01T00:00:00-06:00Oct 2006 |
|
 |
Designing for 1.5V, Low-Power FBDIMMsDesigning for 1.5V, Low-Power FBDIMMs
- Discusses memory power trends and identifies new low-voltage solutions for high-density DDR2 memory designs |
TN-47-22 |
2008-02-01T00:00:00-07:00Feb 2008 |
|
 |
Updated JEDEC DDR2 Specifications (mods too)Updated JEDEC DDR2 Specifications (mods too)
- Covers the updated JEDEC specifications for systems using the initial DDR2-400 and DDR2-533 parts |
TN-47-06 |
2004-08-01T00:00:00-06:00Aug 2004 |
|
 |
DDR2 Posted CAS# Additive Latency (both)DDR2 Posted CAS# Additive Latency (both)
- Describes the AL function of the DDR2 SDRAM device |
TN-47-10 |
2004-12-01T00:00:00-07:00Dec 2004 |
|
 |
DDR2 Redundant Data Strobe (RDQS)DDR2 Redundant Data Strobe (RDQS)
- Describes how to enable the redundant data strobe (RDQS) |
TN-47-12 |
2004-12-01T00:00:00-07:00Dec 2004 |
|
 |
DDR2 tCKE Power-Down RequirementDDR2 tCKE Power-Down Requirement
- Describes the tCKE timing parameter of DDR2 SDRAM |
TN-47-14 |
2004-12-01T00:00:00-07:00Dec 2004 |
|
 |
Design Guide for Two-DIMM, Unbuffered SystemsDesign Guide for Two-DIMM, Unbuffered Systems
- DDR2-533 memory design guide for two-DIMM, unbuffered systems |
TN-47-01 |
2004-10-01T00:00:00-06:00Oct 2004 |
|
 |
DDR2 Simulation Support DDR2 Simulation Support
- Covers DDR2 simulation, adding to Micron's extensive array of design support tools for system designers |
TN-47-07 |
2004-08-01T00:00:00-06:00Aug 2004 |
|
 |
DDR2 SDRAM Bank AddressingDDR2 SDRAM Bank Addressing
- Describes the evolution in array architecture from DDR to DDR2 SDRAM |
TN-47-09 |
2004-12-01T00:00:00-07:00Dec 2004 |
|
 |
DDR2 Differential DQS FeatureDDR2 Differential DQS Feature
- Describes the differential DQS function of the DDR2 SDRAM |
TN-47-11 |
2004-12-01T00:00:00-07:00Dec 2004 |
|